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 SL74HC14
Hex Schmitt-Trigger Inverter
High-Performance Silicon-Gate CMOS
The SL74HC14 is identical in pinout to the LS/ALS14, LS/ALS04. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC14 is useful to "square up" slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the SL74HC14A finds applications in noisy environments. * * * * Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC14N Plastic SL74HC14D SOIC TA = -55 to 125 C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
Inputs A L H PIN 14 =VCC PIN 7 = GND Output Y H L
SLS
System Logic Semiconductor
SL74HC14
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr , t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 2.0 0 -55 Max 6.0 VCC +125 No Limit* Unit V V C ns
* When VIN 50% VCC , ICC > 1mA
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs mu st be left open.
SLS
System Logic Semiconductor
SL74HC14
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 1.0 2.3 3.0 0.9 2.0 2.6 0.3 0.9 1.2 1.2 2.25 3.0 0.2 0.4 0.5 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 1.0 85 C 1.5 3.15 4.2 0.95 2.25 2.95 0.95 2.05 2.65 0.3 0.9 1.2 1.2 2.25 3.0 0.2 0.4 0.5 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 10 125 C 1.5 3.15 4.2 0.95 2.25 2.95 0.95 2.05 2.65 0.3 0.9 1.2 1.2 2.25 3.0 0.2 0.4 0.5 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 40 A A V Unit
VT+max
Maximum PositiveGoing Input Threshold Voltage Minimum PositiveGoing Input Threshold Voltage Maximum NegativeGoing Input Threshold Voltage Minimum NegativeGoing Input Threshold Voltage Maximum Hysteresis Voltage Minimum Hysteresis Voltage Minimum High-Level Output Voltage
VOUT=0.1 V IOUT 20 A VOUT=0.1 V IOUT 20 A VOUT=VCC -0.1 V IOUT 20 A VOUT=VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VINVT -min IOUT 20 A VINVT -min IOUT4mA IOUT5.2mA
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.5 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
V
VT+min
V
VT-max
V
VT-min
V
VHmax Note 1 VHmin Note 1 VOH
V
V
V
VOL
Maximum Low-Level Output Voltage
VINVT +max IOUT 20 A VINVT +max IOUT 4mA IOUT5.2mA
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
VIN=VCC or GND VIN=VCC or GND IOUT=0A
Note: 1 VHmin>(VT+min)-(VT-max); VHmax=(VT+max)-(VT-min) .
SLS
System Logic Semiconductor
SL74HC14
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns)
VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance V 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 95 19 16 75 15 13 10 85C 120 24 20 95 19 16 10 125C 145 29 25 110 22 19 10 Unit ns
tTLH, t THL
ns
CIN
pF
Power Dissipation Capacitance (Per Inverter) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
Typical @25C,VCC=5.0 V 22 pF
Figure 1. Switching Waveforms
Figure 2. Test Circuit
SLS
System Logic Semiconductor


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